1. Field of the Invention
The present invention relates to an error correction device for performing error correction of a received signal having an error correcting code (parity), such as a radio data system (RDS) broadcasting signal or FM multiplex broadcasting signal.
2. Description of the Related Art
In the receiving of a broadcasting signal, the received signal generally has noise due to interference, such as fading, occurring in a transmission. Consequently, when the received signal is demodulated to digital data by a demodulating circuit, bits of the demodulated digital data cannot always correctly be judged to be zero or one. In a conventional RDS receiver or FM multiplex receiver, therefore, errors in data demodulated by the demodulating circuit are corrected to improve correctness of the data.
Although a bit is originally one and the level of the bit is near unity, a conventional demodulating circuit judges the bit to be zero when the level is below one. When the error correctability of an error correcting circuit covers the number and positions of such erroneous bits, the errors are completely corrected. However, if the number and positions are beyond the range of error correctability, the error correction becomes impossible. For example, the error correcting circuit of an RDS receiver can correct five erroneous bits when the interval of the erroneous bits is five bits or less, but cannot even correct two erroneous bits when the interval becomes more than five bits. This is because this error correction circuit is designed for correcting a burst error which includes consecutive error bits.